介绍
除法都已经很熟悉了。这里我主要是使用fpga来实现一下除法器的功能。我这里使用的算法是,首先将除数进行左移n位,如果被除数比左移后的除数还要大,说明商的第n位是1,大家可以理解或者验证一下。
设计文件
library ieee;
use ieee.std_logic_1164.all;
entity divider is
generic(n : integer := 3);
port( a,b : in integer range 0 to 15;
quo : out std_logic_vector (3 downto 0);
remain : out integer range 0 to 15;
err : out std_logic);
end entity;
architecture behavior of divider is
begin
process(a,b)
variable temp1 : integer range 0 to 15;
variable temp2 : integer range 0 to 15;
begin
temp1 := a;
temp2 := b;
if(b=0)then
err <= '1';
else
err <= '0';
end if;
for i in n downto 0 loop
if(temp1 >= temp2*2**i) then
quo(i) <= '1';
temp1 := temp1 - temp2*2**i;
else
quo(i) <= '0';
temp1 := temp1;
end if;
end loop;
remain <= temp1;
end process;
end architecture;
测试文件
library ieee;
use ieee.std_logic_1164.all;
entity tb_divider is
generic(n : integer := 3);
end entity;
architecture behavior of tb_divider is
component divider is
port( a,b : in integer range 0 to 15;
quo : out std_logic_vector (3 downto 0);
remain : out integer range 0 to 15;
err : out std_logic);
end component;
signal a,b,remain : integer range 0 to 15;
signal quo : std_logic_vector (3 downto 0);
signal err : std_logic;
begin
dut : divider
port map(a,b,quo,remain,err);
process
begin
a <= 8;
b <= 5;
wait for 20ns;
b <= 0;
wait for 20ns;
a <= 13;
b <= 2;
wait for 20ns;
end process;
end architecture;
仿真结果
结语
从仿真的结果中可以看出,我添加了err信号用来判断除数是否为0,如果除数为0,那么err信号就输出高电平。
有什么问题大家留言吧。