ZKP学习笔记
ZK-Learning MOOC课程笔记
Lecture 15: Secure ZK Circuits via Formal Methods (Guest Lecturer: Yu Feng (UCSB & Veridise))
15.2 Formal Methods in ZK (Part I)
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Circuits Workflow
- Source Code: Witness Generation and Constraints
- Witness Generation and Constraints should (generally) be equivalent!
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What is Equivalence
- Every input-output of P must satisfy C
- Every (x,y) which satisfies C must be an input-out pair of P
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Equivalence Violations
- Underconstrained Bugs: Verifier can accept bad inputs/ outputs
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A Taxonomy of ZK Bugs
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Unconstrained Signals
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Corresponds to signals whose constraints always evaluate to true, accepting everything
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Example: Underconstrained Output
- Error: for (var i = 0; i< n, i++)
- No constrains over the last element of output
- Attacker can pass in any value for out 2
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Unsafe Component Usage
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Sub-circuits often assume constraints are placed on inputs and outputs
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Corresponds to cases where the use of a sub-circuit does not follow
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Example: Under-Constrained Sub-Circuit Output
- Missing constraint lt.out === 0
- Without the missing constraint, attackers can withdraw more funds than they have
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Constraint/Computation Discrepancy
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Not all computation can be directly expressed as a constraint
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Corresponds to constraints that do not capture a computation’s semantics
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Example: No Zero Inverse
- Accepts arbitrary out when a and b are 0!
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Circuit Dependence Graphs (CDG)
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Goal: Identify discrepancies between computation and constraints
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Data dependence <–
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Constrain ===
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CDG Example
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- Vanguard Framework