目录
模型机下载FPGA设计
框架
仿真
代码
MIOC.v
IO.v
SoC.v
模型机下载FPGA设计
32位MIPS地址空间采用内存与IO统一编址方式，总共232个存储单元，每个单元默认存放1个字节，即总共4GB。划分为:用户空间和内核空间。
（1）内核空间（0x8000_0000—0xFFFF_FFFF）2GB
（2）用户空间（0x0000_0000—0x7FFF_FFFF）2GB
框架
仿真
instmem [0] = 32'h34011100; //ori r1,r0,1100h r1--32'h0000 1100
instmem [1] = 32'h34020020; //ori r2,r0,0020h r2--32'h0000 0020
instmem [2] = 32'h3403ff00; //ori r3,r0,ff00h r3--32'h0000 ff00
instmem [3] = 32'h3404ffff; //ori r4,r0,ffffh r4--32'h0000 ffff
//R1=00001100 R2=00000020
instmem [4] = 32'b000000_00001_00010_00101_00000_100000;//add,R5,R1,R2 00001120
instmem [5] = 32'b000000_00001_00010_00110_00000_100101;//or,R6,R1,R2 00001120//测试FPGA
//用户空间的访问0000_0000~6FFF_FFFF
//(r1)=0000 1100
// +0000 0018
//addr=0000 1118
// =1000100011000 字节地址
// =100 0100 0110 字地址
// =446H 只有1K空间 太大电脑内存不够 实际大小有7000_0000
// =46H 丢掉了高位的1位
// =70
//datamem[70]=(r6)=00001120
instmem[6]=32'b101011_00001_00110_0000_0000_0001_1000; //sw r6,0x18(r1)
//(r7)=datamem[70]
instmem[7]=32'b100011_00001_00111_0000_0000_0001_1000; //lw r7,0x18(r1)
//IO空间的访问7000_0000~7FFF_FFFF
//lui R0,7000 --R8 --70000000
instmem [8] = 32'h3C087000;
//(r8)=70000000
// +0000 0018
//addr=7000 0018
// =0111 0000 0000 0000 0000 0000 0001 1000 字节地址
// =0111 0000 0000 0000 0001 0000 0001 10 字地址
// =1C00 0406H 只有1K空间 实际大小有1000_0000
// =06H 丢掉了多余位 1K=400H
// =6
//iomem[6]=(r6)=00001120
instmem[9]=32'b101011_01000_00110_0000_0000_0001_1000; //sw r6,0x18(r8)
//(r9)=iomem[6]
instmem[10]=32'b100011_01000_01001_0000_0000_0001_1000; //lw r9,0x18(r8)
代码
MIOC.v
`include "define.v"
module MIOC(
input wire memCe,
input wire memWr,
input wire [31:0] memAddr,
input wire [31:0] wtData,
input wire[31:0] ramRdData,
input wire[31:0] ioRdData,
output reg[31:0] rdData,
output reg ramCe,
output reg ramWe,
output reg [31:0] ramAddr,
output reg[31:0] ramWtData,
output reg ioCe,
output reg ioWe,
output reg[31:0] ioAddr,
output reg [31:0] ioWtData
);
always@(*)
if(memCe == `RamEnable)
// if(memAddr & 32'hF000_0000 == 32'h7000_0000) //按位与结果不对
if(memAddr >= 32'h7000_0000 && memAddr<32'h8000_0000)
begin
ioCe= `RamEnable;
ioWe = memWr;
ioAddr = memAddr;
ramCe= `RamDisable;
ramWe = `RamUnWrite;
ramAddr = `Zero;
end
else
begin
ioCe = `RamDisable;
ioWe= `RamUnWrite;
ioAddr = `Zero;
ramCe= `RamEnable;
ramWe = memWr;
ramAddr = memAddr;
end
else
begin
ioCe= `RamDisable;
ioWe= `RamUnWrite;
ioAddr = `Zero;
ramCe= `RamDisable;
ramWe = `RamUnWrite;
ramAddr = `Zero;
end
always@(*)
if(memCe == `RamEnable)
if(ramCe ==`RamEnable)
begin
rdData= ramRdData;
ramWtData = wtData;
ioWtData= `Zero;
end
else
begin
rdData = ioRdData;
ramWtData= `Zero;
ioWtData=wtData;
end
else
begin
rdData= `Zero;
ramWtData= `Zero;
ioWtData= `Zero;
end
endmoduleIO.v
`include "define.v";
module IO(
input wire ce,
input wire clk,
input wire we,
input wire[31:0]addr,
input wire[31:0]wtData,
output reg[31:0]rdData
/*IO interface*/
);
/*access IO device*/
reg [31:0] iomem [1023 : 0];
always@(*)
if(ce == `RamDisable)
rdData = `Zero;
else
rdData = iomem[addr[11 : 2]];
always@(posedge clk)
if(ce == `RamEnable && we == `RamWrite)
iomem[addr[11 : 2]] = wtData;
else ;
endmodule
SoC.v
module SoC(
input wire clk,
input wire rst
);
wire [31:0] instAddr;
wire [31:0] instruction;
wire romCe;
//ls
wire memCe, memWr;
wire [31:0] memAddr;
wire [31:0] rdData;
wire [31:0] wtData;
//interupt
wire[5:0] intr;
wire intimer;
assign intr={5'b0,intimer};
//FPGA
wire ramCe,ramWe,ioCe,ioWe;
wire[31:0] ramWtData,ramAddr,ramRdData;
wire[31:0] ioWtData,ioAddr,ioRdData;
MIPS mips0(
.intr(intr),//
.intimer(intr[0]),//
.clk(clk),
.rst(rst),
.instruction(instruction),
.instAddr(instAddr),
.romCe(romCe),
.rdData(rdData),
.wtData(wtData),
.memAddr(memAddr),
.memCe(memCe),
.memWr(memWr)
);
MIOC mioc0(
.memCe(memCe),
.memWr(memWr),
.memAddr(memAddr),
.wtData(wtData),
.rdData(rdData),
.ramCe(ramCe),
.ramWe(ramWe),
.ramAddr(ramAddr),
.ramRdData(ramRdData),
.ramWtData(ramWtData),
.ioCe(ioCe),
.ioWe(ioWe),
.ioAddr(ioAddr),
.ioRdData(ioRdData),
.ioWtData(ioWtData)
);
InstMem instrom0(
.ce(romCe),
.addr(instAddr),
.data(instruction)
);
/*
//DataMem
DataMem datamem0(
.ce(memCe),
.clk(clk),
.we(memWr),
.addr(memAddr),
.wtData(wtData),
.rdData(rdData)
);
*/
DataMem datamem0(
.ce(ramCe),
.clk(clk),
.we(ramWe),
.addr(ramAddr),
.rdData(ramRdData),
.wtData(ramWtData)
);
IO io0(
.ce(ioCe),
.clk(clk),
.we(ioWe),
.addr(ioAddr),
.rdData(ioRdData),
.wtData(ioWtData)
);
endmodule
