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本篇文章继续介绍Verdi的实用技巧；

2 Verdi实用技巧-Part2

2.1 Dump波形常用的task

FSDB: Fast Signal Data Base(就是快速的波形文件): The FSDB stores the simulation results in an effcient and compact format foramt;
使用system tasks对verilog/VHDL设计文件来dump values into FSDB during simulation.

2.1.1 Frequently Used Dump Tasks

• $fsdbDumpfile:Specify FSDB File Name and limit the FSDB file size; 用来设置名字和限制FSDB文件大小；

----$fsdbDumpfile("chip.fsdb");
----$fsdbDumpfile("chip.fsdb",1000);

• $fsdbDumpSVA: Dump SVA results into FSDB;

----$fsdbDumpSVA;
----$fsdbDumpSVA(1,system.arbiter);
----$fsdbDumpSVA(system.arbiter,"+fsdbfile=SVA.fsdb");

• $fsdbDumpVars: Dump signal value changes of specified Instances and depth;

----$fsdbDumpvars;
----$fsdbDumpvars("+fsdbfile+my.fsdb");
----$fsdbDumpvars(0,system.i_cpu);
----$fsdbDumpvars(0,system,"+fsdbfile+novas.fsdb");

• fsdbDumpon–$fsdbDumpoff --Turn on/off FSDB dumping;
  $ $fsdbAutoSwitchDumpfile–Limit FSDB file size and switch dumping to new FSDB file;
  ----option + no_overwrite: stop dumping into the file when the file number hits the restriction.

----$fsdbDumpoff("+fsdbfile+rtl.fsdb");
----#5us;
----$fsdbDumpon("+fsdbfile+rtl.fsdb");

• $fsdbSuppress -suppress unwanted signals or scopes during dump;
  ----must be specified before $fsdbDumpvars,$fsdbDumpvarsByFile,$fsdbDumpMDA;Otherwise $fsdbSuppress will not work.

--$fsdbSuppress(instance[,instance]*);	//instance means scope or signal
--$fsdbSuppress("suppress_file");
--$fsdbSuppress("file=",file_name|file_var);
--$fsdbSuppress("module_file=",module_file_name|module_file_var);

• $fsdbAutoSwitchDumpfile: limit the fsdb file size and switch dumping to new FSDB file automatically.
  ---- option +no_overwrite: stop dumping into the file when the file number hits the restriction.

--$fsdbAutoSwitchDumpfile(200,"my.fsdb",10); # automatically switch to a new dump file when the working FSDB size reaches 200MB;Totally keep 10 fies;
--$fsdbAutoSwtichDumpfile(1000,aaa,10,"+no_overwrite");
----FSDB file are:
-- aaa_000.fsdb
-- aaa_001.fsdb
-- aaa_002.fsdb
-- ...fsdb
-- aaa_009.fsdb

----Stop dumping;

2.1.2 Demo

写一个Dump tasks 的Demo.

initial begin
	$fsdbSuppress(system.i_pram);
	$fsdbDumpvars;
	$fsdbDumpvars(0,system.i_cpu.i_ALUB,"+fsdbfile+My.fsdb");
	#5000
	$fsdbDumpoff("+fsdbfile+my.fsdb");
	#2000
	$fsdbDumpon("+fsdbfile+my.fsdb");
	#5500
	$finish;
end

//--$VERDI_HOME/demo/verilog/rtl/system.v

2.2 提取波形信息小工具–FSDB Utilities

• fsdbdebug: dump the FSDB info and generate a log file for debugging;
• vcd2fsdb: convert VCD into FSDB;
• fsdb2vcd: convert FSDB into VCD;
• vfast: convert Verilog,Spice,xp,rawfile,wfm, and VCD files to FSDB files;
• fsdbextract: extract signals,scopes,time periods from existed FSDB without re-simulatiing.
• fsdbreport: generate a report of value of value changes for specified signals.
• fsdbedit: modify scope hireachies in the FSDB file.

#使用 utility -h # for a list of all options or $VERDI_HOME/doc/verdi.pdf

Demo:

fsdbdebug novars.fsdb -info

2.3 Debug in Source code view

nTrace User Interface: The nTraceMain window is a souce code viewer and analyzer that operates on KDB to display the design hierarchy,signals and source code(Verilog,VHDL,SV and SystemC) for selected design blocks.

• Design Browser Pane;
• Signal List Pane;
• Source Code View;
• Message Pane;

2.3.1 Find Scopes By Find Scope form

To search for instances by Module name; Source–>Find Scope to open the form.

2.3.2 Go to line in Souce code View

• HotKey:G–>go te line;
• Go to 1st Executable command;
  

2.3.3 Use Bookmarks for Source Code

直接使用快捷键：

• 设置BookMark: ctrl+F2;
• Previous BookMark: Shift+F2;
• Next BookMark: F2;

2.3.4 Identify False Logic

Turn on the View–>Identify False Logic toggle in nTrace.non-active logics will be grayed out in Source Code View.

2.3.5 Source Code Folding

Source code folding make it easier to understand and view complex designs.

2.4 反标宏–Annotate Macro

When debugging designs that contain `define macros, it is often helpful to view a macro defination in the context of a macro reference.

• show tip when moving the cursor over a macro.
• Source -> Expand Macro(M key)to show macro info.

2.5 Verdi UVM debug Advanced Tech

• Highlight for the whole Verdi:selecte signals in any window. invoke RMB–>Highlight command.the color will be appied to any window.
• View Signal Values on SouceCode window. Source–>Active Annotation(X keys).
• Add to waveform : Drap and Drop the signal.
• 开启多线程启动Verdi

setenv FFR_MT_THREAD_COUNT 2
lscpu # for view the cpu core.

2.5.1 Trace this value

• trace Drives and Loads:这个是最经常用的，这就不用多说；debug的入门基本功；
• Temporal Flow View: select a signal in source code pane,click the “create Temporal Flow View”; one command for the root cause.
  

trace this value to locate the cause of a specific value.

2.5.2 Trace X

right-click–>trace x;

2.5.3 Auto Trace

use Verdi for tracing signals.