【Altera】Cyclone10 FPGA DDR3使用

开发板

硬件

框图

原理图

测试工具

DDR IP核配置

调试及遇到的问题

读写仲裁时序

问题1.拉高read后，wait一直没反应

问题2.DDR校正不过的一个可能性

延伸学习

开发板

Intel官方提供c10的开发套件：Intel® Cyclone® 10 GX FPGA Development Kit，很有参考价值。

官方手册

《Intel® Cyclone® 10 GX FPGA Development Kit User Guide》

《c10gx-dev-SDI-SCH》

硬件

框图

图中可见EMIF接口位宽40bit，933MHz。

英特尔Cyclone 10 GX FPGA器件支持高达933 MHz的DDR3内存。在此开发套件中，使用DDR3器件实现了933 MHz的DDR3 x40。EMIF在同一列中使用连续的bank。为了达到933 MHz的速度，EMIF使用bank 2J和2K来支持933 MHz的40位宽度。信号定义符合EMIF约束。

原理图

由图可见共使用了3片IS43TR16256A-107MBLI，有一片只使用了8bit，所以共16+16+8=40bit。

测试工具

官方提供测试程序Board test system，可测试ddr

The following sections describe the controls on the DDR3 tab.

Start

Initiates DDR3 memory transaction performance analysis.

Stop

Terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected

since you last clicked Start:

• Write, Read and Total performance bars: Shows the percentage of maximum

theoretical data rate that the requested transactions are able to achieve.

• Write (MBps), Read(MBps) and Total(MBps): Show the number of bytes of

data analayzed per second.

Error

ControlThis control displays data errors detected during analysis and allows you to inserterrors:

• Detected: Displays the number of data errors detected in the hardware.

• Inserted: Displays the number of errors inserted into the transaction stream.

• Insert: Inserts a one-word error into the transaction stream each time you click

the button. Insert Error is only enabled during transaction performance analysis.

• Clear: Resets the Detected errors and Inserted errors counters to zeroes.

Address Range (Bytes)

Determines the number of bytes to use in each iteration of reads and writes.